Bootstrap augmentation circuit and method
US5894241A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01714
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and disposed between first and second capacitor terminals. A non-overlapping signal generator is formed from a pair of NOR gates, and an inverter, to generate a pair of control signals CS1, and CS2 wherein when one of the control signals is active, the other control signal is inactive. Four n-channel transistors are provided in a switching matrix. One pair of the four n-channel transistors responds to control signal CS2 to connect the capacitor formed by the n-channel transistor across and between ground, and the output pad. In this switched configuration, a voltage level on the output pad is effectively impressed upon the capacitor, and is stored thereon. When an input signal to the buffer changes state to a logic high signal, the output of the control signals also change state, wherein the two n-channel transistors previously conducting, are now turned OFF, and the other two of the four n-channel transistors, which are controlled by…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.