System and method for robust clocking schemes for logic circuits
US5894419A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1997 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Apr 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method according to the present invention for mapping a clocking scheme to determine robust clocking schemes in a logic circuit is disclosed. The circuit can be represented by a clocking graph, the clocking graph having at least one loop including a plurality of vertices, wherein two vertices represent each relevant signal, one for a rising edge and one for a falling edge. Additionally, a plurality of constraints of the logic circuit propagate through circuit delays. The method according to the present invention comprises the steps of selecting one of the vertices as a reference; assigning at least one of the plurality of vertices as an unknown; creating at least a first equation by setting the unknown as not equal to any of the other vertices for each constraint, the first equation being included in a set of equations; creating at least a second equation by setting a sum of times between edges equal to a number of phases in a cycle, the second equation representing the at least one loop in the clocking graph, wherein the second equation is also included in the set of equations; and solving the set of equations to provide a set of clocking schemes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.