Semiconductor memory device equipped with an equalizing control circuit having a function of latching an equalizing signal
US5894442A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1997 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Feb 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor memory device which, while preventing an operation error, achieves the shortening of a precharging time and, hence, further shortening of a cycle time of a memory operation. The equalizing control circuit includes a latch circuit. An equalizing control circuit receives a signal WLact and a signal X-ADR from a predecoder and outputs an equalizing signal EQS from these two signals. A latch circuit in the equalizing control circuit is set (the inactivation of an equalizing signal) by a signal X-ADR which is activated with an internal RAS signal and holds its state. The latch circuit is reset (the activation of the equalizing signal) by a signal corresponding to a word line active signal WLact with a word line inactivated. By doing so, it is possible to provide the equalizing control circuit not directly depending upon the internal RAS signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.