Method and apparatus for controlling I/O channels responsive to an availability of a plurality of I/O devices to transfer data
US5894560A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1996 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Aug 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to chain contiguous DMA scatter gather sub blocks of a PRD table for channel 0 with contiguous DMA scatter gather sub blocks of a PRD table for channel 1, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled based on the availability of data from the I/O device's buffer memory, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.