Doping technique for MOS devices
US5895238A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Dec 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
Abstract
A method for manufacturing a semiconductor device having impurity doped regions serving as source and drain and a semiconductor device obtained by the application of the same method are disclosed. In the method, a semiconductor substrate having a gate oxide is prepared, and a gate electrode is formed on the gate oxide. A first dielectric film is formed on the semiconductor substrate impurity ions of a first conductive type into the semiconductor substrate while permitting the gate electrode and the first dielectric film formed on the side walls of the gate electrode to serve as self-aligning masks. Then, a second dielectric film to be deposited on the first dielectric film, and an anisotropic etching is effected on at least on the second dielectric film to form on the side walls of the gate electrode spacers having a prescribed profile. Thereafter, impurity ions of a second conductive type are implanted into the semiconductor substrate while permitting the gate electrode and the spacers to serve as self-aligning masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.