Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts

US5895239A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventors

• Erik S. Jeng · Taipei, TW
• Hung-Yi Luo · New Taipei, TW

Key dates

• Filing date: Sep 14, 1998
• Grant date: Apr 20, 1999
• Expiry date: Sep 14, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

DRAM cells having self-aligned node-contacts-to-bit lines with tungsten landing plug contacts for reduced aspect ratio contact openings and via holes is achieved. A planar insulating layer is formed, and openings for bit line contacts, node contacts, and landing plugs on the chip periphery are concurrently etched. A W/TiN layer is patterned to form bit lines, capacitor node, and multilevel contact landing plugs on the DRAM chip. The landing plugs reduce the aspect ratio of the openings for the multilevel contacts. Bit line sidewall spacers are formed, and a BPSG is deposited and planarized. Capacitor openings are etched in the BPSG aligned over the node contacts. A conformal conducting layer is deposited, and a polymer is deposited and planarized. The polymer and the conducting layer are polished back to complete the capacitor bottom electrodes in the capacitor openings. The polymer is removed. An inter-electrode dielectric layer and a conformal conducting layer (top electrode) are deposited and patterned to complete the capacitors. Capacitor openings are filled with a planarized insulator and the interlevel contact openings etched to the landing plugs therein have reduced aspect r…