Cache flushing methods and apparatus
US5895488A · kind A · utility
44Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Feb 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for managing a cache which includes a number of dirty lines in which (a) the percentage of dirty lines in the cache is determined, (b) the cache is flushed if the determined percentage of dirty lines exceeds a predetermined threshold, (c) whether a state of a system is idle is determined based on at least two indicators including (i) CPU idle percentage, (ii) data bus busyness percentage, (iii) percentage of dirty lines, and (iv) I/Os per second, and (d) if the state of the system is determined to be idle, a line of the cache is flushed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.