PLL synthesizer having a reset circuit
US5896066A · kind A · utility
19Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1996 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Sep 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL including a phase comparator, a VCO, and a charge pump further includes a reset circuit. The reset circuit detects whether both of the charge pump transistors are in an ON state, and if so, generates a reset signal which inhibits the UP and DOWN signals generated by the phase comparator. The reset circuit includes first and second detection circuits and a signal generating circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.