System and method for maintaining network synchronization utilizing digital phase comparison techniques with synchronous residual time stamps
US5896427A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1998 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Jul 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5674
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value. The clock generation stage adjusts the transmit clock in response to a filtered control value and transmits the source data to the destination CPE at the adjusted transmit clock frequency. By maintaining a constant…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.