Method of resistless gate metal etch for fets
US5897366A · kind A · utility
2Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1997 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Mar 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3086
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.