Pseudo-random address generation mechanism that reduces address translation time
US5897662A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is known that virtual memory segments that are allocated together tend to be used together. With existing sequential address allocation mechanisms, this in turn means that programs tend to end up using the same set or sets of virtual segment addresses (i.e., in the same minitable or minitables), which, as mentioned, leads to increased address translation time because of clumping. The address allocation mechanism of the present invention reduces clumping by allocating virtual segment addresses in a pseudo-random order. This decreases the likelihood that virtual segment addresses that are allocated together end up in the same set or sets of virtual segment addresses within the address translation table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.