Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner
US5897667A · kind A · utility
16Cited by
21References
52Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1996 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Nov 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.