Semiconductor memory having redundant memory cell array
US5898627A · kind A · utility
9Cited by
1References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 15, 1998 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Jul 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To make a read/write test on a redundant memory and to realize the detection of faults of the redundant memory cell array in advance, there are provided a first control circuit which inhibits the activation of word lines for selecting a normal memory cell array in response to a test signal and a second control circuit which activates redundant word lines for selecting a redundant memory cell array in response to the test signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.