Patent · US Expired

Hierarchical memory system for microcode and means for correcting errors in the microcode

US5898867A · kind A · utility

3Cited by

19References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Klaus J. Getzlaff · Schenefeld, DE
Johann Hajdu
Brigitte Roethe · Eppelheim, DE
Udo Wille · Holzgerlingen, DE

Key dates

Filing date	Oct 6, 1993
Grant date	Apr 27, 1999
Priority date	—
Expiry date	Oct 6, 2013

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1008
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A multiprocessor computer system includes a system clock, a main memory connected through a memory bus to a microinstruction memory and a microinstruction decoder. Circuitry detects whether the microinstruction being decoded is the wrong microinstruction or has a parity error. On detection of such an erroneous microinstruction, the microinstruction is reloaded from the main memory into the microinstruction memory and then passed to the microinstruction decoder without interrupting the system clock or operation of the other processors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.