CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time interval
US5898894A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.