System and method for controlling data transmission rates between circuits in different clock domains via selectable acknowledge signal timing
US5898895A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 1996 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Oct 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing speed-regulated data transmission between two synchronous systems in different clock domains. A first synchronous circuit includes a memory device, and a second synchronous circuit includes one or more data-requesting devices. The first synchronous circuit operates at a greater clock speed than the clock speed of the second synchronous circuit. A read request buffer queues read request signals from the data-requesting devices, and outputs one of the read request signals to the memory device. A pulse generator receives the read request signal which was output from the queue, and generates a plurality of signal pulses in response thereto. Each of the pulses occurs at a different predetermined time from the occurrence of the read request signal. One of the pulses is selected to be the read acknowledge signal, and assertion of the read acknowledge signal allows the read request buffer queue to output another read request signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.