Direct current (DC) offset compensation method and apparatus
US5898912A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/3052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiver (300) includes input (I.sub.in), output (V.sub.out), forward path with filter (104, and 108), and feedback path with error amplifier (112) coupled into the forward path. Coupled to the feedback path is an error signal storage device (408, 508). A control circuit (320) responsive to input signal amplitude couples to the storage device (408, 508) and retrieves stored error signal information for use by the feedback path. During calibration, a forward path stage is stimulated with a plurality of signals of known amplitude to generate outputs (V.sub.out). The outputs are compared to a reference to generate error signals. Error signal values are stored in memory as a function of input signal amplitude. A plurality of error signal values are stored. During operation, stage input signals are detected and compared with the plurality of signals of known amplitude. Upon detection of a match, the error signal value associated with the signal of interest is retrieved from memory and employed during DC offset compensation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.