Delay control circuit
US5900754A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Sep 24, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Sep 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.