Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell
US5901089A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1998 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Apr 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3431
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory system having memory cells capable of storing multiple bits per memory cell is described. The memory system has a restoring operation in which a memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge within the predetermined levels. The memory system also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erased memory cells for increasing the spread, and safety margins, between the predetermined levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.