Method and apparatus for maintaining message order in multi-user FIFO stacks
US5901291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1996 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Oct 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9031
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital parallel processing system wherein a plurality of nodes communicate via messages sent over an interconnection network. Messages are maintained in strict chronological order even though sent by nodes where several sources are generating messages simultaneously. A network adapter is described for interconnecting the processor and its associated memory to a network over a bus. The adapter includes an adapter associated memory programmable into a plurality of functional areas, said functional areas including a send FIFO for storing and forwarding messages to said network from said processor; a stack list for queueing in strict message order activation commands for said send FIFO; and an adapter program area for storing adapter program instructions which control the storing of messages to said send FIFO; and control means responsive to said stack list for executing said adapter program instructions in said strict message order without processor intervention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.