Semiconductor device

US5903053A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Tadashi Iijima · Yokohama, JP
• Hisako Ono · Yokohama, JP
• Kyoichi Suguro · Yokohama, JP
• Yasushi Akasaka · Yokohama, JP
• Shinichi Nakamura · Gifu, JP

Key dates

• Filing date: Jul 9, 1996
• Grant date: May 11, 1999
• Expiry date: Jul 9, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A semiconductor device comprising a conductive layer and an amorphous alloy layer formed on the bottom surface of said conductive layer and acting as a barrier layer. The conductive layer is either an electrode layer or a wiring layer. The amorphous alloy layer is made of a matrix phase and microcrystal grains. The matrix phase consists mainly of a Ti--Si--N amorphous alloy. The microcrystal grains are dispersed in the matrix phase, not continuously arranged in the direction of thickness of the amorphous alloy layer.