Semiconductor device and memory system
US5903495A · kind A · utility
455Cited by
4References
44Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1997 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Mar 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data items read from said memory cells, wherein data items read from said memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits, during data-reading operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.