Multi-bank synchronous semiconductor memory device
US5903514A · kind A · utility
36Cited by
1References
11Claims
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Assignee
Inventor
Key dates
| Filing date | Mar 12, 1998 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Mar 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multi-bank semiconductor memory device, if only one bank is in the active state, a bank drive signal generating circuit supplies, operation mode designation signals corresponding to an operation mode instruction signal supplied from a command decoder according to array activation signals from bank driving circuits provided corresponding to banks respectively, to the bank driving circuit provided for the bank in the active state. The state of the bank address signal is arbitrary. Accordingly, control of bank designation in the multi-bank semiconductor memory device is simplified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.