Method and apparatus for translating a conditional instruction compatible with a first instruction set architecture (ISA) into a conditional instruction compatible with a second ISA
US5903760A · kind A · utility
45Cited by
5References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1996 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Jun 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for increasing the performance of binary translated conditional instructions. According to one embodiment of the invention, a conditional instruction compatible with the first ISA is decoded. The condition of the conditional instruction is dependent on at least on status flag. The conditional instruction is translated to be compatible with a second ISA, wherein the condition of the conditional instruction is altered to be dependent on a previously computed difference between two values, the difference residing in a memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.