Interconnection technique for hybrid integrated devices
US5904495A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Jun 11, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hybrid integrated circuit and method of fabricating a hybrid integrated circuit. A first wafer is provided having a first surface with a first electrical contact for a first active circuit associated therewith and a second surface. A second wafer is provided having a third surface with a second electrical contact for a second active circuit associated therewith and a fourth surface, the second wafer being chemically thinned at the fourth surface. The first and second wafers are bonded together at an interface between the first and third surfaces such that the first and second electrical contacts are relatively aligned with one another. The fourth surface of the second wafer is processed to define an access via to both the first and second contacts. An electrical interconnection is formed between the first and second contacts within the access via so that the first and second active circuits are electrically interconnected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.