Unbuffered latch resistant to back-writing and method of operation therefor
US5905393A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Oct 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop. As will be appreciated, because only two extra transistors are needed, the present invention has improved performance while consuming very little silicon area, power, and adding almost no delay to the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.