CMOS integrated circuit regulator for reducing power supply noise
US5905399A · kind A · utility
19Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/467
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A CMOS integrated circuit regulator for mixed mode integrated circuits reduces digital switching noise through use of a clamped dual source follower circuit and a charge reservoir bypass capacitor. Relatively constant current is provided to the CMOS logic during transitions to minimize switching noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.