Auto power down circuit for a semiconductor memory device
US5905688A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1998 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Feb 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power down circuit for a memory device is provided that includes a burn-in voltage detector to generate a burn-in voltage detecting signal to control a power down signal when a burn-in voltage reaches a predetermined level. The power down circuit enhances a burn-in function by operating the memory cells and peripheral circuits for a relatively long time at a high level voltage when a burn-in is performed on the memory device with an auto power down function. Thus, the memory device reliability is also enhanced. The memory device includes a power down timer for generating a power down signal to control an input/output operation of a memory cell in response to a plurality of address transition detecting signals, a plurality of data input detecting signals, a chip select detecting signal, a write mode detecting signal and the burn-in voltage detecting signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.