Data decoding circuit, voltage-controlled oscillation circuit, data decoding system and electronic equipment
US5905759A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Aug 7, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/03
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data decoding circuit of the present invention can regenerate a bit synchronization signal from a data received by using a code such as a split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and transform the received data into a serial binary data. The data decoding circuit includes an edge detection section for detecting a transition point in the received data; a pulse generating section for generating a phase comparing timing signal having a pulse width of substantially 1/(4.times.fs) when fs is a data transfer frequency and a received data regenerating signal having a pulse width of substantially 1(2.times.fs) in synchronism with an output of the edge detection means; a phase synchronization oscillation section synchronized in phase with the phase comparing timing signal for outputting a signal having a frequency n times the data transfer frequency fs; and a sampling section including means for generating the bit synchronization signal by dividing a frequency of a signal outputted from the phase synchronization oscillation means into 1/n, means for sampling the received data regenerating s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.