Fault tolerant memory system
US5905854A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device Lo the output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.