Safestore procedure for efficient recovery following a fault during execution of an iterative execution instruction
US5905857A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Mar 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a safestore memory for storing the contents of the plurality of software visible registers, after a data manipulation operation, is provided. Iterative execution instructions subject to a page fault are specially handled in that, during execution, status information indicative of the ongoing status and valid intermediate results are additionally stored in the safestore memory. Then, in the event of a page fault encountered during the execution of the iterative execution instruction, execution is suspended until access to a valid copy of the missing page is obtained. When a valid copy becomes available, the execution of the iterative execution instruction is restarted at the point at which the valid intermediate results had been obtained prior to occurrence of the page fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.