Multiprocessor system connected by a duplicated system bus having a bus status notification line
US5905875A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Jan 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system having the capability of increasing the speed of a bus clock while retaining high reliability and fault tolerant performance as well as utilizing the current operating system resources. The multiprocessor system is made up of a plurality of processor modules connected together through a duplicated system bus. The duplicated system bus is divided into a plurality of segments, and these segments are coupled together by at least one bus extender mechanism. The multiprocessor system is also provided with first notification means which is provided between bus control mechanisms for controlling the states of physical buses and the bus extender mechanism, and the bus control mechanisms and the bus extender mechanism are mutually notified of the state of each mechanism through the first notification means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.