System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor
US5905913A · kind A · utility
33Cited by
13References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Apr 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt mechanism associated with a peripheral devise is connected to a processor by an interrupt driven I/O bus. The mechanism includes an n input System Interrupt Status Register (SISR) which collects up to n different interrupts from the device during a predetermined time period. Gate and timing circuits under control of signals provided by the processor regulate the frequency of the interrupts thus reducing the number of interrupt operations required to service the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.