Set-associative cache memory utilizing a single bank of physical memory
US5905997A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Oct 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple banks associated with a multiple set associative cache are stored in a single chip, reducing the number of SRAMs required. Certain status information for the second level (L2) cache is stored with the status information of the first level cache. This enhances the speed of operations by avoiding a status look-up and modification in the L2 cache during a write operation. In addition, the L2 cache tag address and status bits are stored in a portion of one bank of the L2 data RAMs, further reducing the number of SRAMs required. Finally, the present invention also provides local read-write storage for use by the processor by reserving a number of L2 cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.