Computer with a cache controller and cache memory with a priority table and priority levels
US5906000A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Feb 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system according to the present invention comprises a processor, a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority corresponding to the frequency of access by the processor to read each of the data items, a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority corresponding to each of the data items, and a controller including means for obtaining, when a cache miss has occurred, a priority corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor, and means for comparing the obtained priority with a priority of data stored in a predetermined cache block in the cache memory, thereby to determine whether or not data replacement should be performed in the predetermined cache block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.