Continuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check
US5907566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1997 |
| Grant date | May 25, 1999 |
| Priority date | — |
| Expiry date | May 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5673
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A continuous byte stream encoder/decoder process where a continuous stream of ATM data cells is received with a plurality of words, where each word has a plurality of bits in parallel. The ATM data cell is analyzed and new control words are created to convey information such as Start-of-Cell, parity and synchronization signals for the serializer and deserializer chip set. These control words are combined with the data words of the ATM data cell to form a combined word stream. This word stream having a higher word transfer rate than the original ATM data cell. This combined word stream is fed to a known 8B/10B encoder which further modifies the data for proper transmission over an AC coupled serial path. Data from the 8B/10B decoder is then serialized through known serialization/deserialization chip sets passed over the serial path and then deserialized back into an recombined word stream. This word stream is decoded both with a 8B/10B decoder and with a frequency decreasing decoder to restore the data to its original data cell format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.