Dynamic random access memory circuit and methods therefor

US5909388A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventor

• Gerhard Mueller · Meitingen, DE

Key dates

• Filing date: Mar 31, 1998
• Grant date: Jun 1, 1999
• Expiry date: Mar 31, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/1006
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory circuit having a stitched architecture wherein word lines of the memory circuit comprise a low resistance conductor stitched to a gate conductor portion having a higher resistance than the low resistance conductor. The memory circuit includes an array of memory cells having thereon bit lines disposed generally along a first direction and the word lines disposed generally along a second direction substantially orthogonal to the first direction. The memory circuit also includes an array sense amplifier region disposed adjacent the array of memory cells generally along the first direction. The array sense amplifier region has therein a plurality of array sense amplifiers coupled to the bit lines. The memory circuit further includes a stitch region containing contacts for stitching the low resistance conductor with the gate conductor. The stitch region is disposed adjacent the array of memory cells generally along the second direction. There is further included a set of local data lines disposed generally along the second direction and coupled to the plurality of array sense amplifiers. There is also included a set of master data switches coupled to the set of local data lines…