Bit synchronizing circuit
US5909473A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1997 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Feb 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a bit synchronizing circuit, the oscillating operation is prevented in the phase synchronizing stage such that even the reception data including a phase variation such as a jitter component can be appropriately reproduced. A phase comparator compares the phase of reception data with that of each of the n-phase clock signals to produce clock phase information. An averaging circuit obtains mean value data of the clock phase information. D-type flip flop circuits achieve sampling operations of the reception data and latch therein n sampling data items to be thereafter outputted. A data selector selects one of the n sampling data items according to the mean value data of clock phase information and delivers therefrom the selected item as selection data. A clock selector selects one of the n-phase clock signals in association with the average data of clock phase information and then outputs the selected item as an extraction clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.