Error detection and correction for data stored across multiple byte-wide memory devices
US5909541A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1996 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Jun 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1633
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital computing system includes a first and second processor clocked for locked step operation. A shared memory stores a linear block codeword across a plurality of byte-wide memory devices. The codeword includes a first dataword and a second dataword. Each of the first and second datawords includes an equal plurality of databits and each includes an equal plurality of checkbits associated therewith. First error detection and correction logic connected to the first processor receives the first dataword and checkbits associated therewith of the codeword addressed by the first processor and a second dataword and checkbits associated therewith of the codeword addressed by the second processor. First error detection and correction logic detects and/or corrects errors in the codeword. Second error detection and correction logic connected to the second processor receives the second dataword and checkbits associated therewith of the codeword addressed by the second processor and the first dataword and checkbits associated therewith of the codeword addressed by the first processor. The second error detection and correction logic detects and/or corrects errors in the codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.