Low power serial arbitration system
US5909558A · kind A · utility
Inventors
Key dates
| Filing date | Jul 31, 1997 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Jul 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/374
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial arbitration system for arbitration between multiple processors (20, 21, 22) in a low power system has an arbitration line driven by each of the processors and received by each of the other processors. The arbitration lines (30, 31, 32) are coupled to arbitration ports (60, 61, 62, 63, 64) on each processor (20, 21, 22) numbered from zero for the driven arbitration port (60). Each of the processors (20, 21, 22) has a processor ID number, with a master processor (20) having ID zero. The arbitration line (30) driven by the master processor (20) is coupled to each other processor (21, 22) on the arbitration port (61', 62') numbered equal to the processor ID of that other processor (21, 22). The driven arbitration lines (31, 32) from the other processors (21, 22) are coupled to the arbitration ports (61, 62) on the master processor (20) corresponding to the processor ID of the driving processor (21, 22). Arbitration ports (63, 64) on the master processor (20) not driven by another processor (21, 22) are coupled to its arbitration line (30), while the remaining ports (63', 64') on the other processors (21, 22) are coupled to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.