Multi-port ethernet frame switch
US5909564A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/45
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An Ethernet switch which includes a plurality of medium access control (MAC) interface logic circuits each coupled to an associated output port operative to perform serial-to-parallel conversion for frames being received from an associated output port and parallel-to-serial conversion for frames being transferred to an associated output port and other interfacing functions. The switch has an internal bus, a buffer memory coupled to each of the MAC interface logic circuits at one end and to the internal bus at another end, a switch central processor coupled to the internal bus and a multi-channel Direct Memory Access (DMA) Controller coupled to the internal bus and to the switch central processor, operative to transfer incoming frames to an external memory and to transfer frames stored temporarily in external memory to their destination in accordance with instructions from the switch central processor. An external memory controller is coupled to the DMA Controller and to an external memory port. An expansion bus interface logic circuit is coupled to said DMA Controller and to an expansion bus port. The switch central processor performs frame address handling and controls transfer of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.