Processor architecture with divisional signal in instruction decode for parallel storing of variable bit-width results in separate memory locations
US5909588A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.