Method for testing data retention in a static random access memory using isolated V.sub.cc supply
US5910922A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1997 |
| Grant date | Jun 8, 1999 |
| Priority date | — |
| Expiry date | Aug 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method for providing a power supply voltage to a memory circuit during a memory data retention test are provided. In such a circuit, a first power supply terminal and a second power supply terminal are provided together with a plurality of circuit elements, which are coupled to form a current path between the first and second power supply terminals, such that each circuit element contributes a predetermined voltage drop between the first and second power supply terminals when a current flows in said current path. In addition, a shunt device having a control terminal and coupled across one or more of said circuit elements is provided. The control terminal receives a control signal, such that when the control signal is asserted, the shunt device equalizes a voltage across said one or more of said circuit elements. The memory circuit draws its power supply voltage from the second power supply terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.