Parallel processing building block chip
US5911082A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1997 |
| Grant date | Jun 8, 1999 |
| Priority date | — |
| Expiry date | Feb 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processing building block (PPBB) chip comprises a low performance programmable digital signal processor (DSP) to implement relatively low intensity processing functions and includes a bus control for address and data communication. A medium performance programmable DSP to implement relatively medium intensity processing functions and includes a bus control for address and data communication. A high performance programmable DSP to implement relatively high intensity processing functions and includes a bus control for address and data communication. A serial and parallel bus controller provides external connectivity to a host system bus. A data router controller is connected to the bus control of each of the high, medium and low DSP's, and to the bus controller, and includes a memory interface controller for connection to an external RAM system, and a data router for controlling data movement between any of the high, medium and low DSP's, the memory interface controller, the bus controller as well as to other PPBB chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.