Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming
US5912488A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 24, 1997 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Jun 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first "source-side" region of second conductivity type (e.g., P+) and a second "drain-side" region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate. During programming, this EEPROM unit cell provides efficient mid-channel injection at high rates and at relatively low voltage levels and avoids many of the limitations associated with conventional stacked-gate EE…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.