Quiescent current monitor circuit for wafer level integrated circuit testing
US5912562A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1997 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Feb 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A current monitor circuitry for detecting defects in a semiconductor device through performance of quiescent current testing. The circuitry for performing quiescent current testing may be implemented on chip or in an expendable portion of the wafer or a combination of both. In one embodiment, a quiescent current monitor unit interfaces with the circuit to be tested. The quiescent current monitor includes a sense amplifier and a level detector. The sense amplifier senses for a voltage differential and the level detector checks for a predetermined voltage rise. The voltage differences may be used for verification of specified circuit operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.