Method and apparatus for fast checking the frame check sequence of a segmented message
US5912881A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1996 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Nov 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5652
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A process and an apparatus to calculate the FCS (Frame Check Sequence) error checking code of a message sent over a connection and segmented into a finite number of packets in a fixed size packets network. The process is implemented in the adapter cards of the ATM network access nodes (2, 4) located at the boundary of the ATM network. These nodes, when supporting AAL5 type ATM connections, reassemble messages which have been segmented at the entry of the network and to calculate the FCS of the message cell payloads for data integrity checking. The process of the invention starts at each reception of a cell with the calculation of a partial FCS (10) performed in parallel to the connection control block fetching phase (40); these 2 parallel operations allow FCS checking during the cell processing time of connections established over medium and high speed lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.