Method and system for testing self-timed circuitry
US5912900A · kind A · utility
9Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1996 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Dec 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
From a first circuit, information is output in response to acknowledgement signals. From a second circuit, the acknowledgement signals are output in response to the second circuit receiving portions of the information from the first circuit. The portions and the acknowledgement signals are output asynchronously with respect to one another. With at least one of the first and second circuits, a signal having a logic state is received, the logic state is latched, and an operation is performed in response to the latched logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.