High speed communication between high cycle rate electronic devices using a low cycle rate bus
US5913075A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1997 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Mar 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for communicating information from a high speed digital device, such as a processor, to a high speed peripheral device over a bus which has a frequency capability materially lower than the clock rates of the respective sending and receiving devices. Multiple successive digital signals are latched, converted to analog format current source signals, transmitted over the bus in analog format, decoded into respective digital format signals at the receiving end of the bus, and sequentially provided to the peripheral device in the original order. Analog to digital and digital to analog conversion accuracy is maintained through the use of a linking current reference which defines at each end of the bus a reference signal suitable for mirrored replication. The current mirrors allow accurate integrated circuit device dimension controlled current generation and corresponding current level decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.