Method of manufacturing an insulaed gate transistor
US5913111A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1996 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Jan 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides a transistor manufacture method comprising the steps of forming, on a semiconductor substrate, an insulating film being made open at least in an introducing portion through which an impurity for forming a drain region other than a lightly-doped region is introduced, then forming a gate electrode and a drain electrode each containing an impurity, and then introducing the impurity through between the gate electrode and the drain electrode to thereby form the lightly-doped region; and introducing the impurity from the drain electrode through the impurity introducing portion with heat treatment, to thereby form the drain region. A transistor manufactured by the above method is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.